1. Field of the Invention
The present invention relates to a method for fabricating a liquid crystal display device, and more particularly, to a method for fabricating a thin film transistor as a switching device of LCD by only four masks without using a diffraction mask.
2. Discussion of the Related Art
A liquid crystal display device includes a thin film transistor (TFT) array substrate on which a plurality of thin film transistors are arranged in a matrix form, a color filter substrate facing the TFT array substrate for displaying an image in color, and a liquid crystal layer filled into the space between the substrates.
Processes for forming the thin film transistor substantially affect the performance of the liquid crystal display device. A process for fabricating a thin film transistor (TFT) of a liquid crystal display device will be described with reference to FIGS. 1A to 1E.
A process of fabricating a TFT is typically performed by either a five-mask process or a four-mask process. FIGS. 1A to 1E are views illustrating a process of fabricating a thin film transistor using five masks.
As illustrated in FIG. 1A, a metal is deposited on a transparent substrate 1 such as a glass. In general, the metal is formed by a sputtering method. After forming the metal, photoresist (not shown) is deposited on the metal layer. By means of photolithography using a first mask (now shown), a gate electrode 2a in a channel region, a first storage electrode 2b in a storage region and a gate pad pattern 2c are formed.
Subsequently, as illustrated in FIG. 1B, a gate insulating layer 3 of silicon oxide or silicon nitride is formed on the substrate on which the gate electrode 2a, the first storage electrode 2b and gate pad pattern 2c are formed, and a semiconductor layer is formed on the gate insulating layer 3. Then, by means of photolithography using a second mask (not shown), an active layer 4 is defined on the channel region. The active layer 4 may include an amorphous silicon layer forming channel and a high impurity doped semiconductor layer for ohmic contact characteristics. The gate insulating layer 3 and the active layer 4 may generally be formed by a plasma enhanced chemical vapor deposition (PECVD) method.
After forming the active layer, as illustrated in FIG. 1C, a conductive layer is formed on the active layer and the gate insulating layer 3. The conductive layer is patterned to form a source and drain electrodes 5 and 6 at the channel region, a second storage electrode 7 at the storage region, and a data pad pattern 8 at a data pad portion by a photolithography process using a third mask (not shown).
Next, as illustrated in FIG. 1D, a passivation layer 9 on the source and drain electrodes 5 and 6 is formed by photolithography using a fourth mask (not shown). Contact holes are formed on the passivation layer to expose the drain electrode 6 at the channel region, the second storage electrode 7, the gate pad pattern 2c and the data pad pattern 8.
After forming the contact holes on the passivation layer, as illustrated in FIG. 1E, a transparent electrode material is sputtered. A pixel electrode 10 connected to the drain electrode 6 at the channel region and to the second storage electrode 7 at the storage region is formed by photolithography using a fifth mask (not shown) in conjunction with the transparent electrode materials. The transparent electrode materials are selectively etched to form a gate pad 11 connected to the gate pad pattern 2c at the gate pad portion and a data pad 12 connected to the data pad pattern 8.
The method for fabricating a liquid crystal display device according to the related art has a problem that there are limits to reduction of fabrication costs and simplification of processes due to multiple photolithography procedures corresponding to five masks.
A related art solution to this problem involves a method for fabricating a liquid crystal display device using four masks, which is described below in reference to FIGS. 2A to 2G.
As illustrated in FIG. 2A, after depositing electrode materials on a substrate 21, a gate electrode 22a, a storage electrode 22b and a gate pad pattern 22c are selectively formed on a channel region, a storage region and a gate pad portion on the substrate 21, respectively. In addition, as illustrated in FIG. 2B, a gate insulating layer 23 of silicon oxide or silicon nitride is formed on the substrate; a semiconductor layer 24 is formed on the gate insulating layer 23; and a conductive layer 25 is formed on the semiconductor layer 24, sequentially. The semiconductor layer 24 may be a dual layer of amorphous silicon (a-Si) and a semiconductor layer doped with high density impurities.
Next, as illustrated in FIG. 2C, a photoresist 26 is deposited on the conductive layer 25 and subsequently patterned using a second mask 27. The resulting photoresist pattern 26a remains at the channel region, the storage region, and the data pad portion. In particular, diffraction exposure is radiated onto the photoresist 26a formed at the gate electrode 22a to form a stepped photoresist pattern having a thin center portion. As a result of the diffraction exposure, the photoresist on the channel region has a stepped shape such that the photoresist on the channel region is thinner than that on source and drain regions, thereby two-step processes exposing the channel region and forming source and drain electrodes may be performed. As also illustrated in FIG. 2D, the conductive layer 25 and the gate insulating layer 24 are partially removed by the photoresist pattern 26a formed by the diffraction exposure to define the channel region, a second storage electrode 25b and a data pad pattern 25c. 
Next, as illustrated in FIG. 2E, the photoresist 26a on the channel region is ashed and selectively removed. As a result, a conductive layer 25a on the channel is exposed. As illustrated in FIG. 2F, drain electrodes 28 and 29 are formed by etching the conductive layer 25a using the photoresist pattern 26a as an etching mask, and the photoresist pattern 26a is stripped.
Referring to FIG. 2G, a passivation layer 30 is formed on an entire surface of the substrate. Then, through use of photolithography and a third mask (not shown), contact holes are formed in the passivation layer 30 to expose the drain electrode 29, the second storage electrode 25b, the gate pad pattern 22c, and the data pad pattern 25c. 
Next, as illustrated in FIG. 2H, transparent electrode materials are formed on an upper portion of the result, and a pixel electrode 31 is formed by performing photolithography using a fourth mask (not shown). The transparent electrode materials are selectively etched to form a gate pad 32 connected to the pattern for gate pad 22c and a data pad 32 connected to the data pad pattern 25c at the same time.
As so far described, a method for fabricating a liquid crystal display device using four masks may reduce fabrication costs and simplify processes in comparison to a method for fabricating a liquid crystal display device using five masks. However, since a diffraction mask used for the four-mask process is an expensive element, the diffraction mask causes fabrication costs of a thin film transistor to increase.